Chapter 1

Verilog Introduction

Chapter 2

Verilog Basic Architecture

Chapter 3

Data Conversion

Chapter 4

Verilog Operator

Chapter 5

Condition

Chapter 6

Case

Chapter 7

For loop

Chapter 8

Blocking/Non-blocking

Final Examination

Final Examination 1 (V_FEX1)

Grammar-Concept Understanding Problem (GUP)

Basic Programming (V_GUP1)

Value Trace Problem (VTP)

Basic Programming (V_VTP1)

Element Fill-in-blank Problem (EFP)

Basic Programming (V_EFP1)

Flip Flop & Sequential Logic Circuit (V_EFP2)

Code Amendment Problem (CAP)

Basic Programming (V_CAP1)